Verification
Storage Application
- A72 based multi core
- Multiple clusters
- Cache coherent Interconnect with PCIE ports
- DMA
- Secure boot verification using simulator and emulator
- ARM subsystem bring up
- System MMU APIs and configurations
- Core-sight debug IP
- Verification using C & SV-UVM, DAP-ML
Formal Verification
- Formal feasibility check
- Formal planning / testplan
- Implementation of constraints, checkers and covers – hand coded
- Complexity reduction techniques implementations
- Jasper scoreboard integration and coverage app
- Packetizer, width reduction module , Debug IP , AXI interconnect Arbitration , Arm Q channel interface
Xtensa base TRxC
- Ownership of full chip integration, physical design, Analog design and functional verification
- Multi master environment (Xtensa, Jtag and STI)
- Test bench, Test planning and coding (C, SV, UVM)
- Code coverage, Functional Coverage
- GLS
- Physical Design and Analog Design activities
