Physical Design
64 Core Packet Processor
- 7nm design of 15mmx15mm
- Ownership from RTL to GDSII
- Physical design Architectural exploration
- Fullchip planning and integration
- Timing Constraint development
- IP Core hardening
- Block shaping and bus planning
- IO ring design and Bump planning
Solid State Processor
- 16nm design of 9mm x 9mm
- Ownership from netlist to GDSII
- Power gated , multi voltage low power design
- Fullchip floorplan
- Feedthrough insertion
- Repeater flop planning
- Constraint and UPF ownership
- Several Analog hard IP integration
- CLP/MVRC/MVSIM closure
- High frequency signoff
