FPGA & Emulation
Serdes Hard IP Validation
- Serdes validation on a test chip
- PMA & PCS features
- 1.25 to 12.5Gbps data transfers
- Debug features : Eye monitor, PMA debug PRBS pattern gen
- CTLE/DFE functions
- 8b10b (PCIe, JESD)
- 64b66b (CPRI)
- 64b67b (Interlaken)
- Developed IP validation platform to validate IP features
- Embedded processor-based system for control interface
Interlaken IP Validation
- IP validation and compliance check for a new FPGA Device
- Define and develop user models using Interlaken IP @6.375G
- Flow control, Burst Max/short/Min validation
- Per Channel traffic generation and check
- Protocol compliance and InterOp with third party DIGI120G (PMC Sierra) board
- Performance analysis
