Networking – Front End
Data Centre Switching ASIC for Automotive
- Micro-architecture of multiple design blocks
- RTL implementation of blocks - Line ports’ aggregation, L2/L3 Parser, Forwarding Engine (Classification, Filtering, Learning, Aging, CoS, Multicast, Broadcast, Mirroring etc.), Traffic Management/Metering, Queue Manager, Egress Scheduler (DWRR, Strict Priority)
- From scratch – methodology SV/UVM
- Synopsys VIP integration for 1GE/10GE MAC testing
- Compliance testing and PICS Proforma update
Automotive Gateway solution
- CAN/FlexRay Over Ethernet
- Owned complete feasibility study and product specification
- Worked out all commercials and technical details for the productization
- Defined the high-level system architecture – both HW and SW layers
- Upcoming steps – detailed architecture and microarchitecture documents, RTL development and IP integration, Design Verification, FPGA prototyping
Port expansion & Stats @50G , 100G
- Developed complete solution on Xilinx Virtex7 US device
- 100G Data path with two XLAUI interfaces at FPGA. And, 1G/5G ports at line side
- 2x50G XLAUI interface for statistics interface
- Timing closure at ~312.5MHz
- Device selection for the end solution, pin location definitions and on-board validation
- Interfaced with Board design team, SW team at system level
